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SC28L92 3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
Product specification Supersedes data of 1999 May 07 IC19 Data Handbook 2000 Jan 21
Philips Semiconductors
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
DESCRIPTION
The SC28L92 is a pin and function replacement for the SCC2692 and SC26C92 operating at 3.3 or 5 volts supply with added features and deeper FIFOs. Its configuration on power up is that of the SC26C92. Its differences from the 2692 are: 16 character receiver, 16 character transmit FIFOs, watch dog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts. (Neither the SC26C92 nor the SCC2692 is being discontinued.) Pin programming will allow the device to operate with either the Motorola or Intel bus interface. The bit 3 of the MR0a register allows the device to operate in an 8 byte FIFO mode if strict compliance with the SC26C92 FIFO structure is required. The Philips Semiconductors SC28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and DMA interface. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 28 fixed baud rates; a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems. Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full. Also provided on the SC28L92 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. The SC28L92 is available in two package versions: a 44-pin PLCC and 44-pin plastic quad flat pack (PQFP).
* 16-bit programmable Counter/Timer * Programmable baud rate for each receiver and transmitter
selectable from: - 28 fixed rates: 50 to 230.4k baud - Other baud rates to MHz at 16X - Programmable user-defined rates derived from a programmable counter/timer - External 1X or 16X clock
* Parity, framing, and overrun error detection * False start bit detection * Line break detection and generation * Programmable channel mode
- Normal (full-duplex) - Automatic echo - Local loop back - Remote loop back - Multi-drop mode (also called `wake-up' or `9-bit')
* Multi-function 7-bit input port (includes IACKN)
- Can serve as clock or control inputs - Change of state detection on four inputs - Inputs have typically >100k pull-up resistors - Change of state detectors for modem control
* Multi-function 8-bit output port
- Individual bit set/reset capability - Outputs can be programmed to be status/interrupt signals - FIFO status for DMA interface
* Versatile interrupt system
- Single interrupt output with eight maskable interrupting conditions - Output port can be configured to provide a total of up to six separate interrupt outputs that may be wire ORed. - Each FIFO can be programmed for four different interrupt levels - Watch dog timer for each receiver
* Maximum data transfer rates:
1X - 1Mb/sec, 16X - 1Mb/sec
FEATURES
* Member of IMPACT family: 3.3 to 5.0 volt , -40C to +85C and
68K for 80xxx bus interface for all devices.
* Dual full-duplex independent asynchronous receiver/transmitters * 16 character FIFOs for each receiver and transmitter * Pin programming selects 68K or 80xxx bus interface * Programmable data format
- 5 to 8 data bits plus parity - Odd, even, no parity or force parity - - 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
* Automatic wake-up mode for multi-drop applications * Start-end break interrupt/status * Detects break which originates in the middle of a character * On-chip crystal oscillator * Power down mode * Receiver time-out mode * Single +3.3V or +5V power supply * Powers up to emulate SC26C92
2000 Jan 21
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853-2161 23016
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ORDERING INFORMATION
44-Pin Plastic Quad Flat Pack (PQFP) 44-Pin Plastic Leaded Chip Carrier (PLCC)
2000 Jan 21 Philips Semiconductors DESCRIPTION
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
VCC = +3.3 +5V 10%,
Tamb = -40 to +85C
3 INDUSTRIAL SC28L92A1B SC28L92A1A DRAWING NUMBER SOT187-2 SOT307-2 Product specification
SC28L92
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
PIN CONFIGURATION DIAGRAM 80XXX PIN CONFIGURATION
44 34 7 1 33 PLCC 6 1 40 39
PQFP
11
23 17 18 12 22 Function GND GND INTRN D6 D4 D2 D0 NC OP6 OP4 OP2 OP0 TxDA RxDA x1/clk Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function x2 RESET CEN IP2 IP6 IP5 IP4 VCC VCC A0 IP3 A1 IP1 A2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC A0 IP3 A1 IP1 A2 A3 IP0 WRN RDN RxDB I/M TxDB OP1 OP3 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function OP5 OP7 D1 D3 D5 D7 VSS NC INTRN D6 D4 D2 D0 OP6 OP4 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function OP2 OP0 TxDA NC RxDA X1/CLK X2 RESET CEN IP2 IP6 IP5 IP4 VCC 28 29
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Function A3 IP0 WRN RDN RxDB TxDB OP1 OP3 OP5 OP7 I/M D1 D3 D5 D7
Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SD00671
SD00672
2000 Jan 21
4
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
PIN CONFIGURATION DIAGRAM 68XXX PIN CONFIGURATION
44 34 7 1 33 PLCC 6 1 40 39
PQFP
11
23 17 18 12 22 Function GND GND INTRN D6 D4 D2 D0 NC OP6 OP4 OP2 OP0 TxDA RxDA x1/clk Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function x2 RESETN CEN IP2 IACKN IP5 IP4 VCC VCC A0 IP3 A1 IP1 A2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC A0 IP3 A1 IP1 A2 A3 IP0 R/WN DACKN RxDB I/M TxDB OP1 OP3 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function OP5 OP7 D1 D3 D5 D7 VSS NC INTRN D6 D4 D2 D0 OP6 OP4 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function OP2 OP0 TxDA NC RxDA X1/CLK X2 RESETN CEN IP2 IACKN IP5 IP4 VCC 28 29
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Function A3 IP0 R/WN DACKN RxDB TxDB OP1 OP3 OP5 OP7 I/M D1 D3 D5 D7
Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SD00673
SD00674
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5
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
8 D0-D7 BUS BUFFER
CHANNEL A 16 BYTE TRANSMIT FIFO TRANSMIT SHIFT REGISTER TxDA
RDN WRN CEN A0-A3 RESET 4
OPERATION CONTROL ADDRESS DECODE R/W CONTROL
16 BYTE RECEIVE FIFO WATCH DOG TIMER RECEIVE SHIFT REGISTER MRA0, 1, 2 CRA SRA RxDA
INTERRUPT CONTROL INTRN IMR ISR GP INTERNAL DATABUS CHANNEL B (AS ABOVE) TxDB RxDB
INPUT PORT CHANGE OF STATE DETECTORS (4) IPCR ACR
CONTROL
TIMING BAUD RATE GENERATOR
TIMING
7
IP0-IP6
CLOCK SELECTORS
COUNTER/ TIMER
OUTPUT PORT FUNCTION SELECT LOGIC 8
X1/CLK XTAL OSC X2 CSRA CSRB ACR CTL CTU
OP0-OP7
OPCR OPR
VCC VSS
SD00685
Figure 1. Block Diagram (80XXX mode)
2000 Jan 21
6
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
8 D0-D7 BUS BUFFER
CHANNEL A 16 BYTE TRANSMIT FIFO TRANSMIT SHIFT REGISTER TxDA
R/WN IACKN CEN A0-A3 RESETN 4
OPERATION CONTROL ADDRESS DECODE R/W CONTROL
16 BYTE RECEIVE FIFO WATCH DOG TIMER RECEIVE SHIFT REGISTER MRA0, 1, 2 CRA SRA RxDA
INTERRUPT CONTROL INTRN DACKN IMR ISR IVR INTERNAL DATABUS CHANNEL B (AS ABOVE) TxDB RxDB
INPUT PORT CHANGE OF STATE DETECTORS (4) IPCR ACR
CONTROL
TIMING BAUD RATE GENERATOR
TIMING
6
IP0-IP5
CLOCK SELECTORS
COUNTER/ TIMER
OUTPUT PORT FUNCTION SELECT LOGIC 8
X1/CLK XTAL OSC X2 CSRA CSRB ACR CTL CTU
OP0-OP7
OPCR OPR
VCC VSS
SD00694
Figure 2. Block Diagram (68XXX mode)
2000 Jan 21
7
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL(R))
SYMBOL I/M D0-D7 CEN PIN TYPE I I/O I
SC28L92
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NAME AND FUNCTION Bus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table. Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the D0-D7 lines in the 3-State condition. WRN RDN I I I I Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. Address Inputs: Select the DUART internal registers and ports for read/write operations. A0-A3 RESET Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (High) state. Sets MR pointer to MR1. See Figure 4 Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pullup device. INTRN O I X1/CLK X2 Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11). Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open. Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High; "space" is Low. Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High; "space" is Low. O I I RxDA RxDB TxDA TxDB OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 IP0 IP1 IP2 IP3 IP4 IP5 IP6 O O O O O O O O O O I I I I I I I Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle or when operating in local loop back mode. "Mark" is High; "space" is Low. Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `Mark' is High; `space' is Low. Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated automatically on receive or transmit. Output 1: General-purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated automatically on receive or transmit. Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock output. Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock output, or Channel B receiver 1X clock output. Output 4: General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR[1] output. Output 6: General purpose output or Channel A open-drain, active-Low, TxA interrupt ISR[0] output. Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Input 2: General-purpose input or counter/timer external clock input. Output 5: General-purpose output or Channel B open-drain, active-Low, RxB interrupt ISR[5] output. Output 7: General-purpose output, or Channel B open-drain, active-Low, TxB interrupt ISR[4] output. Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Power Supply: +3.3 or +5V supply input 10% Ground VCC Pwr Pwr GND 2000 Jan 21 8
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA(R))
SYMBOL I/M D0-D7 CEN PIN TYPE I
SC28L92
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NAME AND FUNCTION Bus Configuration: When low configures the bus interface to the Conditions shown in this table. I/O I I I Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the R/WN and A0-A3 inputs. When High, places the D0-D7 lines in the 3-State condition. R/WN Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle. Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN. IACKN DACKN A0-A3 O I I Data Transfer Acknowledge: A3-State active -low output asserted in a write, read, or interrupt acknowledge cycle to indicate proper transfer of data between the CPU and the DUART. Address Inputs: Select the DUART internal registers and ports for read/write operations. RESETN Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (High) state. Sets MR pointer to MR1. See Figure 4 Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pullup. INTRN O I X1/CLK X2 Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11). Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open. Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space" is Low. Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space" is Low. O I I RxDA RxDB TxDA TxDB OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 IP0 IP1 IP2 IP3 IP4 IP5 O O O O O O O O O O I I I I I I Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle or when operating in local loop back mode. "Mark" is High; "space" is Low. Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `Mark' is High; `space' is Low. Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated automatically on receive or transmit. Output 1: General-purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated automatically on receive or transmit. Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock output. Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock output, or Channel B receiver 1X clock output. Output 4: General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR [1] output. Output 5: General-purpose output or Channel B open-drain, active-Low, RxB interrupt ISR[5] output. Output 6: General purpose output or Channel A open-drain, active-Low, TxA interrupt ISR[0] output. Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Input 2: General-purpose input or counter/timer external clock input. Output 7: General-purpose output, or Channel B open-drain, active-Low, TxB interrupt ISR[4] output. Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Power Supply: +3.3 or +5V supply input 10% Ground VCC Pwr Pwr GND 2000 Jan 21 9
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
ABSOLUTE MAXIMUM RATINGS1
SYMBOL Tamb Tstg VCC VS PD PD Operating ambient temperature Storage temperature range Voltage from VCC to GND3 Voltage from any pin to GND3 Package power dissipation (PLCC44) Package power dissipation (PQFP44) Derating factor above 25_C (PLCC44) Derating factor above 25_C (PQFP44) PARAMETER range2 RATING Note 4 -65 to +150 -0.5 to +7.0 -0.5 to VCC +0.5 2.4 1.78 19 14 UNIT C C V V W W mW/C mW/C
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature and voltage range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
VCC = 5V 10%, Tamb = -40C to +85C, unless otherwise specified. LIMITS SYMBOL VIL VIH VIH VOL VOH IIX1PD IILX1 IIHX1 II IOZH IOZL IODL IODH ICC Input low voltage Input high voltage (except X1/CLK) Input high voltage (X1/CLK) Output low voltage Output high voltage (except OD outputs)4 IOL = 2.4mA IOH = -400A VIN = 0 to VCC VIN = 0 VIN = VCC VIN = 0 to VCC VIN = 0 to VCC VIN = VCC VIN = 0V VIN = 0 VIN = VCC CMOS input levels CMOS input levels 7 1 -0.5 -0.5 0.5 25 5 VCC -0.5 0.5 -130 0 -0.5 -8 0.05 0.05 0.05 0.5 0 130 +0.5 +0.5 0.5 2.4 0.8*VCC 1.5 2.4 0.2 0.4 PARAMETER TEST CONDITIONS Min Typ Max 0.8 UNIT V V V V V A A A A A A A A A mA mA
X1/CLK input current - power down X1/CLK input low current - operating X1/CLK input high current - operating Input leakage current: All except input port pins Input port pins5 Output off current high, 3-State data bus Output off current low, 3-State data bus Open-drain output low current in off-state Open-drain output high current in off-state Power supply current6 Operating mode Power down mode
NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns maximum. For X1/CLK, this swing is between 0.4V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Typical values are at +25C, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: CL = 125pF, except open drain outputs. Test conditions for open drain outputs: CL = 125pF, constant current source = 2.6mA. 5. Input port pins have active pull-up transistors that will source a typical 2A from VCC when the input pins are at VSS. Input port pins at VCC source 0.0A. 6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2V and VSS + 0.2V.
2000 Jan 21
10
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
DC ELECTRICAL CHARACTERISTICS1, 2, 3
VCC = 3.3V 10%, Tamb = -40C to +85C, unless otherwise specified. LIMITS SYMBOL VIL VIH VOL VOH IIX1PD IILX1 IIHX1 II IOZH IOZL IODL IODH ICC Input low voltage Input high voltage Output low voltage Output high voltage (except OD outputs)4 X1/CLK input current - power down X1/CLK input low current - operating X1/CLK input high current - operating Input leakage current: All except input port pins Input port pins5 Output off current high, 3-State data bus Output off current low, 3-State data bus Open-drain output low current in off-state Open-drain output high current in off-state Power supply current6 Operating mode Power down mode CMOS input levels CMOS input levels 1 5 5.0 mA mA VIN = 0 to VCC VIN = 0 to VCC VIN = VCC VIN = 0V VIN = 0 VIN = VCC -0.5 -0.5 0.5 -0.5 -8 0.05 0.5 +0.5 +0.5 0.5 A A A A A A IOL = 2.4mA IOH = -400A VIN = 0 to VCC VIN = 0 VIN = VCC VCC-0.5 -0.5 -80 0 0.8*VCC PARAMETER TEST CONDITIONS Min Typ 0.65 1.7 0.2 VCC-0.2 0.05 +0.5 0 80 0.4 Max 0.2*VCC UNIT V V V V A A A
NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns maximum. For X1/CLK, this swing is between 0.4V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Typical values are at +25C, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: CL = 125pF, except open drain outputs. Test conditions for open drain outputs: CL = 125pF, constant current source = 2.6mA. 5. Input port pins have active pull-up transistors that will source a typical 2A from VCC when the input pins are at VSS. Input port pins at VCC source 0.0A. 6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2V and VSS+0.2V.
2000 Jan 21
11
AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A
VCC = 5.0V 10%, Tamb = -40C to +85C, unless otherwise specified.
2000 Jan 21
AC CHARACTERISTICS (5 VOLT) 1, 2, 3
Philips Semiconductors
Transmitter Timing, external clock (See Figure 12)
Clock Timing (See Figure 11)
Interrupt Timing (See Figure 10)
Port
Bus
Reset Timing (See Figure 4)
SYMBOL
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
t*RWD
f*CTC
f*CTC
t*TCS
t*TXD
f*CLK
t*CLK
tRES
t*RW
t*DH
t*DD
t*CH
f*RX
t*RX
t*PD
t*PH
t*DS
t*DA
t*CS
t*AH
t*PS
t*AS
t*DF
f*TX
t*TX
t*IR
t*DI
Timing5
Timing5
(See Figure 5)
(See Figure 9)
Output delay from TxC output pin low to TxD data output
TxD output delay from TxC low (TxC input pin)
TxC frequency (1X)8, 9
TxC frequency (16X)
TxC High or low time (16X)
RxC Frequency (1x)8, 9
RxC Frequency (16X)
RxC high or low time (16X)
C/T Clk (IP2)
C/T Clk (IP2) high or low time (C/T external clock input)
X1/CLK frequency8
X1/CLK high or low time
INTRN (or OP3-OP7 when used as interrupts) negated from:
OP port valid after WRN or CEN high (OPR write cycle)
Port in hold time after RDN high
Port in setup time before RDN low (Read IP ports cycle)
High time between read and/or write cycles5, 7
Data hold time after WRN high
Data bus setup time before WRN or CEN high (write cycle)
RDN or CEN high to data bus invalid7
Data bus floating after RDN or CEN high
RDN low to data bus active6
Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)
WRN, RDN pulse width (Low time)
CEN Hold time from RDN. WRN low
CEN setup time to RDN, WRN low
A0-A3 hold time from RDN, WRN low
A0-A3 setup time to RDN, WRN Low
Reset pulse width
Write IMR (Clear of change interrupt mask bit(s))
Read IPCR (delta input port change interrupt)
Stop C/T command (Counter/timer interrupt
Reset Command (delta break change interrupt)
Write TxFIFO (TxRDY interrupt)
Read RxFIFO (RxRDY/FFULL interrupt)
frequency8
PARAMETER
12 Min 100 0.1 30 30 30 30 15 25 15 20 10 0 0AAA 0 0 0 0 0 0 0AAA 0 0 LIMITS4 3.686 Typ -20 -20 -12 40 10 10 10 20 40 40 40 40 40 40 40 10 17 40 12 18 8 6 6 Max Product specification 30 60 16 16 60 60 60 60 60 60 60 20 55 1 1 8 8
SC28L92
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A
LIMITS4 Typ SYMBOL PARAMETER Min Max UNIT Receiver Timing, external clock (See Figure 13) t*RXS RxD data setup time to RxC high t*RXH tDCR tDAT RxD data hold time from RxC high 50 50 40 40 15 15 8 8 ns ns ns ns ns ns 68000 or Motorola bus timing (See Figures 6, 7, tDCW tCSC 8)10 DACKN Low (read cycle) from X1 High10 DACKN Low (write cycle) from X1 High 20 20 10 DACKN High impedance from CEN or IACKN High CEN or IACKN setup time to X1 High for minimum DACKN cycle 10 NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. 3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF, constant current source = 2.6mA. 4. Typical values are the average values at +25C and 5V. 5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the "strobing" input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. Guaranteed by characterization of sample units. 7. If CEN is used as the "strobing" input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must be negated for tRWD to guarantee that any status register changes are valid. 8. Minimum frequencies are not tested but are guaranteed by design. 9. Clocks for 1X mode should maintain a 60/40 duty cycle or better. 10. Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN low or CEN high completes the write cycle.
60 55 50 45 40 35 Tdd (ns) 30 25 20 15 10 5 0 0 20 40 60 80 100 120 pF 140 160 180 200 220 240 12 pF 30 pF 100 pF 125 pF 230 pF 5.0V @ +25C VCC = 3.3V @ +25C
SD00684
NOTES: Bus cycle times: (80XXX mode): tDD + tRWD = 70ns @ 5V, 40ns @ 3.3V + rise and fall time of control signals (68XXX mode) = tCSC + tDAT + 1 cycle of the X1 clock @ 5V + rise and fall time of control signals Figure 3. Port Timing vs. Capacitive Loading at typical conditions
2000 Jan 21
13
AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A
AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3
VCC = 3.3V 10%, Tamb = -40C to +85C, unless otherwise specified. Transmitter Timing, external clock (See Figure 12) Clock Timing (See Figure 11) Interrupt Timing (See Figure 10) Port Bus Reset Timing (See Figure 4) SYMBOL
2000 Jan 21 Philips Semiconductors t*RWD f*CTC f*CTC t*TCS t*TXD f*CLK t*CLK tRES t*RW t*DH t*DD t*CH f*RX t*RX t*PD t*PH t*DS t*DA t*CS t*AH t*PS t*AS t*DF f*TX t*TX t*IR t*DI Timing5 Timing5 (See Figure 5) (See Figure 9) TxD output delay from TxC low (TxC input pin) TxC frequency (1X)8, 9 TxC frequency (16X) TxC High or low time (16X) RxC Frequency (1x)8, 9 RxC Frequency (16X) RxC high or low time (16X) C/T Clk (IP2) X1/CLK frequency8 X1/CLK high or low time Port in hold time after RDN high High time between read and/or write cycles5, 7 Data hold time after WRN high RDN or CEN high to data bus invalid7 Data bus floating after RDN or CEN high RDN low to data bus active6 WRN, RDN pulse width (Low time) CEN Hold time from RDN. WRN low CEN setup time to RDN, WRN low A0-A3 hold time from RDN, WRN low A0-A3 setup time to RDN, WRN Low Reset pulse width Write IMR (Clear of change interrupt mask bit(s)) Read IPCR (delta input port change interrupt) Stop C/T command (Counter/timer interrupt Reset Command (delta break change interrupt) Write TxFIFO (TxRDY interrupt) Read RxFIFO (RxRDY/FFULL interrupt) frequency8 PARAMETER
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
Output delay from TxC output pin low to TxD data output
C/T Clk (IP2) high or low time (C/T external clock input)
INTRN (or OP3-OP7 when used as interrupts) negated from:
OP port valid after WRN or CEN high (OPR write cycle)
Port in setup time before RDN low (Read IP ports cycle)
Data bus setup time before WRN or CEN high (write cycle)
Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)
14 Min 100 0.1 30 30 30 30 20 25 20 25 10 0 0AAA 0 0 0 0 0 0 0AAA 0 0 LIMITS4 3.686 Typ -20 -20 -15 40 15 10 15 25 40 40 40 40 40 40 50 10 20 15 46 10 16 20 6 8 Max Product specification 30 60 16 16 60 60 60 60 60 60 70 20 75 1 1 8 8
SC28L92
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A
LIMITS4 Typ SYMBOL PARAMETER Min Max UNIT Receiver Timing, external clock (See Figure 13) t*RXS RxD data setup time to RxC high t*RXH tDCR tDAT RxD data hold time from RxC high 50 50 10 10 18 18 10 10 ns ns ns ns ns ns 68000 or Motorola bus timing (See Figures 6, 7, tDCW tCSC 8)10 DACKN Low (read cycle) from X1 High10 DACKN Low (write cycle) from X1 High 25 25 15 DACKN High impedance from CEN or IACKN High CEN or IACKN setup time to X1 High for minimum DACKN cycle 15 NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. 3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF, constant current source = 2.6mA. 4. Typical values are the average values at +25C and 3.3V. 5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the "strobing" input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. Guaranteed by characterization of sample units. 7. If CEN is used as the "strobing" input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must be negated for tRWD to guarantee that any status register changes are valid. 8. Minimum frequencies are not tested but are guaranteed by design. 9. Clocks for 1X mode should maintain a 60/40 duty cycle or better. 10. Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN low or CEN high completes the write cycle. 2000 Jan 21 15
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
Block Diagram
The SC28L92 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the Block Diagram.
TIMING CIRCUITS Crystal Clock
The timing block consists of a crystal oscillator, a baud rate generator, a programmable 16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from a crystal connected across the X1/CLK and X2 inputs. If an external clock of the appropriate frequency is available, it may be connected to X1/CLK. The clock serves as the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the DUART. If an external clock is used instead of a crystal, X1 should be driven using a configuration similar to the one in Figure 11. Nominal crystal rate is 3.6864 MHz. Rates up to 8 MHz may be used.
Data Bus Buffer
The data bus buffer provides the interface between the external and internal data buses. It is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART.
Operation Control
The operation control logic receives operation commands from the CPU and generates appropriate signals to internal sections to control device operation. It contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus.
BRG
The baud rate generator operates from the oscillator or external clock input and is capable of generating 28 commonly used data communications baud rates ranging from 50 to 38.4K baud. Programming bit 0 of MR0 to a "1" gives additional baud rates of 57.6kB, 115.2kB and 230.4kB (531kHz with X1 at 8.5MHz). These will be in the 16X mode. A 3.6864 MHz crystal or external clock must be used to get the standard baud rates. The clock outputs from the BRG are at 16X the actual baud rate. The counter/timer can be used as a timer to produce a 16X clock for any other baud rate by counting down the crystal clock or an external clock. The four clock selectors allow the independent selection, for each receiver and transmitter, of any of these baud rates or external timing signal.
Interrupt Control
A single active-Low interrupt output (INTRN) is provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the Interrupt Mask Register (IMR) and the Interrupt Status Register (ISR). The IMR can be programmed to select only certain conditions to cause INTRN to be asserted. The ISR can be read by the CPU to determine all currently active interrupting conditions. Outputs OP3-OP7 can be programmed to provide discrete interrupt outputs for the transmitter, receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their output buffers are changed to the open drain active low configuration. The OP pins may be used for DMA and modem control as well. (See output port notes).
Counter/Timer
The counter timer is a 16-bit programmable divider that operates in one of three modes: counter, timer, time out. In the timer mode it generates a square wave. In the counter mode it generates a time delay. In the time out mode it monitors the time between received characters. The C/T uses the numbers loaded into the Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper Register (CTUR) as its divisor. The counter/timer clock source and mode of operation (counter or timer) is selected by the Auxiliary Control Register bits 6 to 4 (ACR[6:4]). The output of the counter/timer may be used for a baud rate and/or may be output to the OP pins for some external function that may be totally unrelated to data transmission. The counter/timer also sets the counter/timer ready bit in the Interrupt Status Register (ISR) when its output transitions from 1 to 0. A register read address (see Table 1) is reserved to issue a start counter/timer command and a second register read address is reserved to issue a stop command. The value of D(7:0) is ignored. The START command always loads the contents of CTUR, CTLR to the counting registers. The STOP command always resets the ISR (3) bit in the interrupt status register.
FIFO Configuration
Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be configured to operate at a fill capacity of either 8 or 16 bytes. This feature may be used if it is desired to operate the 28L92 in strict compliance with the 26C92. The 8 byte/16 byte mode is controlled by the MR0[3] bit. A 0 value for this bit sets the 8 bit mode ( the default); a 1 sets the 16 byte mode. The FIFO fill interrupt level automatically follow the programming of the MR0[3] bit. See Tables 3 and 4.
68XXX mode
When the I/M pin is connected to VCC (ground), the operation of the SC28L92 switches to the bus interface compatible with the Motorola bus interfaces. Several of the pins change their function as follows: Ip6 becomes IACKN input RDN becomes DACKN WRN becomes R/WN The interrupt vector is enabled and the interrupt vector will be placed on the data bus when IACKN is asserted low. The interrupt vector register is located at address 0xC. The contents of this register are set to 0x0F on the application of RESETN. The generation of DACKN uses two positive edges of the X1 clock as the DACKN delay from the falling edge of CEN. If the CEN is withdrawn before two edges of the X1 clock occur, the generation of DACKN is terminated. Systems not strictly requiring DACKN may use the 68XXX mode with the bus timing of the 80XXX mode greatly decreasing the bus cycle time.
Timer Mode
In the timer mode a symmetrical square wave is generated whose half period is equal in time to division of the selected counter/timer clock frequency by the 16-bit number loaded in the CTLR CTUR. Thus, the frequency of the counter/timer output will be equal to the counter/timer clock frequency divided by twice the value of the CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be set each time the counter/timer transitions from 1 to 0. (High to low)
2000 Jan 21
16
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
This continues regardless of issuance of the stop counter command. ISR[3] is reset by the stop counter command. NOTE: Reading of the CTU and CTL registers in the timer mode is not meaningful. When the C/T is used to generate a baud rate and the C/T is selected through the CSR then the receivers and/or transmitter will be operating in the 16x mode. Calculation for the number `n' to program the counter timer upper and lower registers is shown below. N=2 x 16 x Baud rate desired/(C/T Clock Frequency Often this division will result in a non-integer number; 26.3 for example. One can only program integer numbers to a digital divider. Therefore 26 would be chosen. This gives a baud rate error of 0.3/26.3 which is 1.14%; well within the ability of the asynchronous mode of operation.
the counter until the next character is received. The counter timer is controlled with six commands: Start/Stop C/T, Read/Write Counter/Timer lower register and Read/Write Counter/Timer upper register. These commands have slight differences depending on the mode of operation. Please see the detail of the commands under the CTLR CTUR Register descriptions.
Time Out Mode Caution
When operating in the special time out mode, it is possible to generate what appears to be a "false interrupt", i.e., an interrupt without a cause. This may result when a time-out interrupt occurs and then, BEFORE the interrupt is serviced, another character is received, i.e., the data stream has started again. (The interrupt latency is longer than the pause in the data stream.) In this case, when a new character has been receiver, the counter/timer will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the interrupt service begins for the previously seen interrupt, a read of the ISR will show the "Counter Ready" bit not set. If nothing else is interrupting, this read of the ISR will return a x'00 character. This action may present the appearance of a spurious interrupt.
Counter Mode
In the counter mode the counter/timer counts the value of the CTLR CTUR down to zero and then sets the ISR[3] bit and sets the counter/timer output from 1 to 0. It then rolls over to 65,365 and continues counting with no further observable effect. Reading the C/T in the counter mode outputs the present state of the C/T. If the C/T is not stopped, a read of the C/T may result in changing data on the data bus.
Communications Channels A and B
Each communications channel of the SC28L92 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter can be selected independently from the baud rate generator, the counter/timer, or from an external input. The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits and outputs a composite serial stream of data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for start bit, stop bit, parity bit (if any), or break condition and sends an assembled character to the CPU via the receive FIFO. Three status bits (Break Received, Framing and Parity Errors) are also FIFOed with each data character.
Timeout Mode
The timeout mode uses the received data stream to control the counter. The time-out mode forces the C/T into the timer mode. Each time a received character is transferred from the shift register to the RxFIFO, the counter is restarted. If a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. This mode can be used to indicate when data has been left in the Rx FIFO for more than the programmed time limit. If the receiver has been programmed to interrupt the CPU when the receive FIFO is full, and the message ends before the FIFO is full, the CPU will not be interrupted for the remaining characters in the RxFIFO. By programming the C/T such that it would time out in just over one character time, the above situation could be avoided. The processor would be interrupted any time the data stream had stopped for more than one character time. NOTE: This is very similar to the watch dog time of MR0. The difference is in the programmability of the delay time and that the watchdog timer is restarted by either a receiver load to the RxFIFO or a system read from it. This mode is enabled by writing the appropriate command to the command register. Writing an `Ax' to CRA or CRB will invoke the timeout mode for that channel. Writing a `Cx' to CRA or CRB will disable the timeout mode. Only one receiver should use this mode at a time. However, if both are on, the timeout occurs after both receivers have been inactive for the timeout period. The start of the C/T will be on the logical or of the two receivers. The timeout mode disables the regular START/STOP counter commands and puts the C/T into counter mode under the control of the received data stream. Each time a received character is transferred from the shift register to the RxFIFO, the C/T is stopped after one C/T clock, reloaded with the value in CTUR and CTLR and then restarted on the next C/T clock. If the C/T is allowed to end the count before a new character has been received, the counter ready Bit, ISR[3], will be set. If IMR [3] is set, this will generate an interrupt. Since receiving a character restarts the C/T, the receipt of a character after the C/T has timed out will clear the counter ready bit, ISR [3], and the interrupt. Invoking the `Set Timeout Mode On' command, CRx=`Ax', will also clear the counter ready bit and stop
Input Port
The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be read by the CPU by performing a read operation at address H'D'. A High input results in a logic 1 while a Low input results in a logic 0. D7 will always read as a logic 1. The pins of this port can also serve as auxiliary inputs to certain portions of the DUART logic, modem and DMA. Four change-of-state detectors are provided which are associated with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High transition of these inputs, lasting longer than 25-50 s, will set the corresponding bit in the input port change register. The bits are cleared when the register is read by the CPU. Any change-of-state can also be programmed to generate an interrupt to the CPU. The input port change of state detection circuitry uses a 38.4 kHz sampling clock derived from one of the baud rate generator taps. This results in a sampling period of slightly more than 25 s (this assumes that the clock input is 3.6864 MHz). The detection circuitry, in order to guarantee that a true change in level has occurred, requires two successive samples at the new logic level be observed. As a consequence, the minimum duration of the signal change is 25 s if the transition occurs "coincident with the first sample pulse". The 50 s time refers to the situation in which the change-of-state is "just missed" and the first change-of-state is not detected until 25 s later.
Output Port
The output ports are controlled from six places: the OPCR, OPR, MR, Command, SOPR and ROPR registers. The OPCR register
2000 Jan 21
17
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register. The content of the OPR register is controlled by the "Set Output Port Bits Command" and the "Reset Output Bits Command". These commands are at E and F, respectively. When these commands are used, action takes place only at the bit locations where ones exist. For example, a one in bit location 5 of the data word used with the "Set Output Port bits" command will result in OPR5 being set to one. The OP5 would then be set to zero (VSS). Similarly, a one in bit position 5 of the data word associated with the "Reset Output Ports Bits" command would set OPR5 to zero and, hence, the pin OP5 to a one (VDD). These pins along with the IP pins and their change of state detectors are often used for modem and DMA control.
has returned to the low state. CTS going high during the serialization of a character will not affect that character. The transmitter can also control the RTSN outputs, OP0 or OP1 via MR2[5]. When this mode of operation is set, the meaning of the OP0 or OP1 signals will usually be `end of message'. See description of the MR2[5] bit for more detail. This feature may be used to automatically "turn around" a transceiver in simplex systems.
Receiver
The SC28L92 is conditioned to receive data when enabled through the command register. The receiver looks for a High-to-Low (mark-to-space) transition of the start bit on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16X clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of the bit time clock (1X clock mode). If RxD is sampled High, the start bit is invalid and the search for a valid start bit begins again. If RxD is still Low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the proper number of data bits and parity bit (if any) have been assembled, and one stop bit has been detected. The least significant bit is received first. The data is then transferred to the Receive FIFO and the RxRDY bit in the SR is set to a 1. This condition can be programmed to generate an interrupt at OP4 or OP5 and INTRN. If the character length is less than 8 bits, the most significant unused bits in the RxFIFO are set to zero. After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received without a stop bit (framing error) and RxD remains Low for one half of the bit period after the stop bit was sampled, then the receiver operates as if a new start bit transition had been detected at that point (one-half bit time after the stop bit was sampled). The parity error, framing error, and overrun error (if any) are strobed into the SR from the next byte to be read from the Rx FIFO. If a break condition is detected (RxD is Low for the entire character including the stop bit), a character consisting of all zeros will be loaded into the RxFIFO and the received break bit in the SR is set to 1. The RxD input must return to high for two (2) clock edges of the X1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. This will usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock.
OPERATION Transmitter
The SC28L92 is conditioned to transmit data when the transmitter is enabled through the command register. The SC28L92 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN. When the transmitter is initially enabled the TxRDY and TxEMPT bits will be set in the status register. When a character is loaded to the transmit FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1) the transmit FIFO is empty and the transmit shift register has finished transmitting the stop bit of the last character written to the transmit FIFO, or 2) the transmitter is disabled and then re-enabled. The TxRDY bit is set whenever the transmitter is enabled and the TxFIFO is not full. Data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. Characters cannot be loaded into the TxFIFO while the transmitter is disabled. The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the TxFIFO, the TxD output remains High and the TxEMT bit in the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared when the CPU loads a new character into the TxFIFO. If the transmitter is disabled it continues operating until the character currently being transmitted and any characters in the TxFIFO, including parity and stop bits, have been transmitted. New data cannot be loaded to the TxFIFO when the transmitter is disabled. When the transmitter is reset it stops sending data immediately. The transmitter can be forced to send a break (a continuous low condition) by issuing a START BREAK command via the CR register. The break is terminated by a STOP BREAK command or a transmitter reset. If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1 must be Low in order for the character to be transmitted. The transmitter will check the state of the CTS input at the beginning of each character transmitted. If it is found to be High, the transmitter will delay the transmission of any following characters until the CTS
Transmitter Reset and Disable
Note the difference between transmitter disable and reset. A transmitter reset stops transmitter action immediately, clears the transmitter FIFO and returns the idle state. A transmitter disable withdraws the transmitter interrupts but allows the transmitter to continue operation until all bytes in its FIFO and shift register have been transmitted including the final stop bits. It then returns to its idle state.
Receiver FIFO
The RxFIFO consists of a First-In-First-Out (FIFO) stack with a capacity of 8 or 16 characters. Data is loaded from the receive shift register into the topmost empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all 8 or 16 stack positions are filled with data. Either of these bits can be selected to cause an interrupt. A read of the RxFIFO outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its associated
2000 Jan 21
18
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
status bits (see below) are `popped' thus emptying a FIFO position for new data. A disabled receiver with data in its FIFO may generate an interrupt (see "Receiver Status Bits", below). Its status bits remain active and its watchdog, if enabled, will continue to operate.
Receiver Time-out Mode
In addition to the watch dog timer described in the receiver section, the counter/timer may be used for a similar function. Its programmability, of course, allows much greater precision of time out intervals. The time-out mode uses the received data stream to control the counter. Each time a received character is transferred from the shift register to the RxFIFO, the counter is restarted. If a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. This mode can be used to indicate when data has been left in the RxFIFO for more than the programmed time limit. Otherwise, if the receiver has been programmed to interrupt the CPU when the receive FIFO is full, and the message ends before the FIFO is full, the CPU may not know there is data left in the FIFO. The CTU and CTL value would be programmed for just over one character time, so that the CPU would be interrupted as soon as it has stopped receiving continuous data. This mode can also be used to indicate when the serial line has been marking for longer than the programmed time limit. In this case, the CPU has read all of the characters from the FIFO, but the last character received has started the count. If there is no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated. The time-out mode is enabled by writing the appropriate command to the command register. Writing an `Ax' to CRA or CRB will invoke the time-out mode for that channel. Writing a `Cx' to CRA or CRB will disable the time-out mode. The time-out mode should only be used by one channel at once, since it uses the C/T. If, however, the time-out mode is enabled from both receivers, the time-out will occur only when both receivers have stopped receiving data for the time-out period. CTU and CTL must be loaded with a value greater than the normal receive character period. The time-out mode disables the regular START/STOP Counter commands and puts the ca/T into counter mode under the control of the received data stream. Each time a received character is transferred from the shift register to the RxFIFO, the C/T is stopped after 1 C/T clock, reloaded with the value in CTU and CTL and then restarted on the next C/T clock. If the C/T is allowed to end the count before a new character has been received, the counter ready bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt. Receiving a character after the C/T has timed out will clear the counter ready bit, ISR[3], and the interrupt. Invoking the `Set Time-out Mode On' command, CRx = `Ax', will also clear the counter ready bit and stop the counter until the next character is received.
Receiver Status Bits
In addition to the data word, three status bits (parity error, framing error, and received break) are also appended to each data character in the FIFO. The overrun error, MR1(5), is not FIFOed. Status can be provided in two ways, as programmed by the error mode control bit in the mode register. In the `character' mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the `block' mode, the status provided in the SR for these three bits is the logical-OR of the status for all characters coming to the top of the FIFO since the last `reset error' from the command register was issued. In either mode reading the SR does not affect the FIFO. The FIFO is `popped' only when the RxFIFO is read. Therefore the status register should be read prior to reading the FIFO. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exits, the contents of the FIFO are not affected; the character previously in the shift register is lost and the overrun error status bit (SR[4]) will be set-upon receipt of the start bit of the new (overrunning) character. The receiver can control the deactivation of RTS. If programmed to operate in this mode, the RTSN output will be negated when a valid start bit was received and the FIFO is full. When a FIFO position becomes available, the RTSN output will be re-asserted (set low) automatically. This feature can be used to prevent an overrun, in the receiver, by connecting the RTSN output to the CTSN input of the transmitting device. If the receiver is disabled, the FIFO characters can be read. However, no additional characters can be received until the receiver is enabled again. If the receiver is reset, the FIFO and all of the receiver status, and the corresponding output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again.
Receiver Reset and Disable
Receiver disable stops the receiver immediately--data being assembled in the receiver shift register is lost. Data and status in the FIFO is preserved and may be read. A re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. A receiver reset will discard the present shift register date, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of the FIFO and re-align the FIFO read/write pointers.
Time Out Mode Caution
When operating in the special time out mode, it is possible to generate what appears to be a "false interrupt", i.e., an interrupt without a cause. This may result when a time-out interrupt occurs and then, BEFORE the interrupt is serviced, another character is received, i.e., the data stream has started again. (The interrupt latency is longer than the pause in the data stream.) In this case, when a new character has been receiver, the counter/timer will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the interrupt service begins for the previously seen interrupt, a read of the ISR will show the "Counter Ready" bit not set. If nothing else is interrupting, this read of the ISR will return a x'00 character.
Watchdog
A `watchdog timer' is associated with each receiver. Its interrupt is enabled by MR0[7]. The purpose of this timer is to alert the control processor that characters are in the RxFIFO which have not been read. This situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt. This counter times out after 64 bit times. It is reset each time a character is transferred from the receiver shift register to the RxFIFO or a read of the RxFIFO is executed.
Multi-drop Mode (9-bit or Wake-Up)
The DUART is equipped with a wake up mode for multi-drop applications. This mode is selected by programming bits
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Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
MR1A[4:3]or MR1B[4:3] to `11' for Channels A and B, respectively. In this mode of operation, a `master' station transmits an address character followed by data characters for the addressed `slave' station. The slave stations, with receivers that are normally disabled, examine the received data stream and `wakeup' the CPU (by setting RxRDY)only upon receipt of an address character. The CPU compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again. A transmitted character consists of a start bit, the programmed number of data bits, and Address/Data (A/D) bit, and the programmed number of stop bits. The polarity of the transmitted A/D bit is selected by the CPU by programming bit MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which identifies the corresponding data bits as data while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which identifies the corresponding data bits as an address. The CPU should program the mode register prior to loading the corresponding data bits into the TxFIFO. In this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RxFIFO if the received A/D bit is a one (address tag), but discards the received character if the received A/D bit is a zero (data tag). If enabled, all received characters are transferred to the CPU via the RxFIFO. In either case, the data bits are loaded into the data FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is enabled.
PROGRAMMING
The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 1. The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems. For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped. Each channel has 3 mode registers (MR0, 1, 2) which control the basic configuration of the channel. Access to these registers is controlled by independent MR address pointers. These pointers are set to 0 or 1 by MR control commands in the command register "Miscellaneous Commands". Each time the MR registers are accessed the MR pointer increments, stopping at MR2. It remains pointing to MR2 until set to 0 or 1 via the miscellaneous commands of the command register. The pointer is set to 1 on reset for compatibility with previous Philips Semiconductors UART software. Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Table 2 for register bit descriptions. The reserved registers at addresses H`02' and H`0A' should never be read during normal operation since they are reserved for internal diagnostics.
Table 1. SC28L92 register addressing READ (RDN = 0), WRITE (WRN = 0)
AAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA AAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAA AAAAA AA
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 Mode Register A (MR0A, MR1A, MR2A) Status Register A (SRA) Reserved Mode Register A (MR0A, MR1A, MR2A) Clock Select Register A (CSRA) Command Register A (CRA) Aux. Control Register (ACR) Rx Holding Register A (RxFIFOA) Tx Holding Register A (TxFIFOA) Input Port Change Register (IPCR) Counter/Timer Upper (CTU) Counter/Timer Lower (CTL) Status Register B (SRB) Reserved 0AA 0 1 1AAAAAAAAAAAAAAA Interrupt Status Register (ISR) Interrupt Mask Register (IMR) C/T Upper Preset Register (CTPU) C/T Lower Preset Register (CTPL) Clock Select Register B (CSRB) Command Register B (CRB) Interrupt vector (68K mode) Mode Register B (MR0B, MR1B, MR2B) Mode Register B (MR0B, MR1B, MR2B) Rx Holding Register B (RxFIFOB) Interrupt vector (68K mode) Input Port (IPR) Tx Holding Register B (TxFIFOB) Misc. register (Intel mode), IVR Motorola mode Start Counter Command Stop Counter Command Misc. register (Intel mode), IVR Motorola mode Output Port Conf. Register (OPCR) Set Output Port Bits Command (SOPR) Reset output Port Bits Command (ROPR) NOTE: 1. The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits) 2000 Jan 21 20
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAA AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA A A AAA A A AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAA A A A AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A
2000 Jan 21
CTPU
ISR - INTERRUPT STATUS REGISTER
IMR - INTERRUPT MASK REGISTER (ENABLES INTERRUPTS)
SR - CHANNEL STATUS REGISTER
CR -COMMAND REGISTER
CSR - CLOCK SELECT REGISTER
MR2 - MODE REGISTER 2
MR1 - MODE REGISTER 1
Table 2. Condensed Register bit formats MR0 - MODE REGISTER 0
Philips Semiconductors
Transmitter FIFO
Receiver FIFO
Command Register
Clock Select
Status Register
Mode Register
The following named registers are the same for Channels A and B
Received Break
RxRTS Control
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
Change Input Port
Change Input Port
WATCHDOG
Channel Mode
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bits 7:6
- COUNTER TIMER PRESET REGISTERS, UPPER
Channel Command codes
Receiver Clock,Select Code
Change Break B
Change Break B
Bits 7:4
Framing Error
RxINT BIT 1
RxINT BIT 2
Bits 7:4
Bit 6
Bit 6
Bit 6
Bit 6
BIT 6
TxFIFOA
RxFIFOA
CRA
CSRA
SRA
MRnA
TxRTS Control
Bit 5
Parity Error
TxFIFOB
RxFIFOB
CRB
CSRB
SRB
MRnB
BIT 5BIT 4
Error Mode
RxRDY B
RxRDY B
Bit 5
TxINT (1:0)
Bit 5
Bit 5
Bit 5
CTSN Enable Tx
8 MSB of the BRG Timer divisor.
W only
R only
W only
W only
R only
R/W
Bit 4
Overrun Error
Disable Tx
TxRDTYB
TxRDTYB
Bit 3
Parity Mode
Bit 4
Bit 4
Bit 4
Bit 4:3
FIFO SIZE
Bits 7:0
BIT 3
21
Counter Ready Counter Ready TxEMT Bit 3 Bit 3 Bit 3 Bit 2
Interrupt vector or GP register
Reset Output Port
Set Output Port
Output Configuration Register
Input Port Register
Counter Timer Preset Lower
Counter Timer Preset Upper
Counter Timer Lower Value
Counter Timer Upper Value
Interrupt Mask Register
Interrupt Status Register
Auxiliary Control Register
Input Port Change Register
These are support functions for both Channels
Enable Tx
Parity Type
Transmitter Clock select code,
BAUD RATE EXTENDED II
Bit 2
BIT 2
Change Break A Change Break A TxRDY Bit 2 Bits 3:0 Bit 2 Bit 2 Bit 1
Enable Tx
Stop Bit Length
Bit 3:0
TEST 2
BIT 1
RxFULL
Bit 1
Bits per Character
RxRDY A RxRDY A Bit 1:0 Bit 1 Bit 1
IVR/GP
Bits
Bits
OPCR
IPR
CTPL
CTPU
CTL
CTU
IMR
ISR
ACR
IPCR
Product specification
SC28L92
Enable Rx
BAUD RATE EXTENDED 1
Bit 0
RxRDY
BIT 0
Bit 0
TxRDY A TxRDY A Bit 0 Bit 0 W W W R W W R R W R W R R/W
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
CTPL - COUNTER TIMER PRESET REGISTER, LOWER
AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A AAAAAAAAAA AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Bits 7:0 8 LSB of the BRG Timer divisor.
ACR - AUXILIARY CONTROL REGISTER AND CHANGE OF STATE CONTROL
Bit 7 Bit 6:4 Bit 3 Bit 2 Baud Group Counter Timer mode and clock select Enable IP3 Enable IP2
Bit 1
Bit 0
Enable IP1
Enable IP0
IPCR - INPUT PORT CHANGE REGISTER
Bit 7 Bit 6 Bit 5 Delta IP3 Delta IP2 Delta IP1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delta IP0
State of IP3
State of IP2
State of IP1
State of IP0
IPR - INPUT PORT REGISTER
Bit 7 Bit 6 State of IP State of IP 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State of IP 5
State of IP 4
State of IP 3
State of IP 2
State of IP1
State of IP 0
SOPR - SET THE OUTPUT PORT BITS (OPR)
Bit 7 Set OP 7 BIT 6 Set OP 6 BIT 5 Set OP 5
BIT 4 Set OP 4
BIT 3 Set OP 3
BIT 2 Set OP 2
BIT 1 Set OP 1
BIT 0 Set OP 0
ROPR - RESET OUTPUT PORT BITS (OPR)
Bit 7 Reset OP 7 BIT 6 Reset OP 6 BIT 5 Reset OP 5 BIT 4 Reset OP 4 BIT 3 Reset OP 3 BIT 2 Reset OP 2 BIT 1 Reset OP 1 BIT 0 Reset OP 0
OPCR OUTPUT PORT CONFIGURATION REGISTER (NOTE OP1 AND OP0 ARE THE RTSN OUTPUT AND ARE CONTROLLED BY THE MR REGISTER)
Bit 7 Configure OP7 BIT 6 Configure OP6 BIT 5 Configure OP5 BIT 4 Configure OP4 BIT(3:2) Configure OP3 BIT(1:0) Configure OP2
REGISTER DESCRIPTIONS Mode Registers MR0A Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.
A A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAA A A A AAAAAA A A AA A AA A AAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A
0x00 0x08 0 = Disable 1 = Enable See Tables in MR0 description See Table 4 0 = 8 byte FIFO 1 = 16 byte FIFO 0 = Normal 1 = Extend II Set to 0 0 = Normal 1 = Extend MR0[7]--This bit controls the receiver watch dog timer. 0 = disable, 1 = enable. When enabled, the watch dog timer will generate a receiver interrupt if the receiver FIFO has not been accessed within 64 bit times of the receiver 1X clock. This is used to alert the control processor that data is in the RxFIFO that has not been read. This situation may occur when the byte count of the last part of a message is not large enough to generate an interrupt. 01 10 11 3 or more bytes in FIFO 6 or more bytes in FIFO 8 bytes in FIFO (Rx FULL)
Addr MR0A/ MR0B
Bit 7 Rx WATCHDOG
BIT 6 RxINT BIT 2
BITS 5:4 TxINT (1:0)
BIT 3 FIFO SIZE
BIT 2 BAUD RATE EXTENDED II
BIT 1 TEST 2
BIT 0 BAUD RATE EXTENDED 1
AAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAA AAAAAAA
MR0[6] MR1[6] 00 01 10 11 Interrupt Condition 1 or more bytes in FIFO (Rx RDY) 8 or more bytes in FIFO MR0[6] MR1[6] Note that this control is split between MR0 and MR1. This is for backward compatibility to the SC2692 and SCN2681. 12 or more bytes in FIFO
MR0[6]--Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1 sets the fill level of the FIFO that generates the receiver interrupt.
Table 3a. Receiver FIFO interrupt fill level(MR0(3)=1 (16 bytes)
Table 3. Receiver FIFO interrupt fill level (MR0(3) = 0 (8 bytes)
MR0[6] MR1[6] 00
16 bytes in FIFO (Rx FULL)
Interrupt Condition
1 or more bytes in FIFO (Rx RDY)
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22
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
For the receiver these bits control the number of FIFO positions filled when the receiver will attempt to interrupt. After the reset the receiver FIFO is empty. The default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it. MR0[5:4]--Tx interrupt fill level.
Table 4. Transmitter FIFO interrupt fill level MR0(3) = 0 (8 bytes)
For the transmitter these bits control the number of FIFO positions empty when the transmitter will attempt to interrupt. After the reset the transmit FIFO has 8 bytes empty. It will then attempt to interrupt as soon as the transmitter is enabled. The default setting of the MR0 bits (5:4) condition the transmitter to attempt to interrupt only when it is completely empty. As soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request. MR0[3]--Selects the FIFO depth at 8 or 16 bytes. See Tables 3 and 4 MR0[2:0]--These bits are used to select one of the six baud rate groups. See Table 5 for the group organization. 000 Normal mode 001 Extended mode I 100 Extended mode II Other combinations of MR2[2:0] should not be used Note: MR0[3:0] are not used in channel B and should be set to 0.
AAAAAAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AA AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAA
AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAA
MR0[5:4] 00 01 10 11 Interrupt Condition 8 bytes empty (Tx EMPTY) 4 or more bytes empty 6 or more bytes empty 1 or more bytes empty (Tx RDY)
Table 4a. Transmitter FIFO interrupt fill level MR0(3) = 1 (16 bytes)
MR0[5:4] 00 01 10 11
Interrupt Condition
16 bytes empty (Tx EMPTY) 8 or more bytes empty
12 or more bytes empty
1 or more bytes empty (Tx RDY)
MR1A Mode Register 1
Addr BIT 7 MR1A/ MR1B
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Rx CONTROLS RTS 0 = No 1 = Yes
RxINT BIT 1
ERROR MODE
PARITY MODE
PARITY TYPE 0 = Even 1 = Odd
BITS PER CHARACTER 00 = 5 01 = 6 10 = 7 11 = 8
0x00 0x08
0 = RxRDY 1 = FFULL
0 = Char 1 = Block
00 = With Parity 01 = Force Parity 10 = No Parity 11 = Multi-drop Mode
NOTE: In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset. MR1A is accessed when the Channel A MR pointer points to MR1. The pointer is set to MR1 by RESET or by a `set pointer' command applied via CR command 1. After reading or writing MR1A, the pointer will point to MR2A.
MR1[6]--Bit 1 of the receiver interrupt control. See description under MR0[6].
MR1A[7]--Channel A Receiver Request-to-Send Control (Flow Control) This bit controls the deactivation of the RTSAN output (OP0) by the receiver. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. Proper automatic operation of flow control requires OPR[0] (channel A) or OPR[1] (channel B) to be set to logical 1. MR1A[7] = 1 causes RTSAN to be negated (OP0 is driven to a `1' [VCC]) upon receipt of a valid start bit if the Channel A FIFO is full. This is the beginning of the reception of the ninth byte. If the FIFO is not read before the start of the tenth or 17th byte, an overrun condition will occur and the tenth or 17th or 17th byte will be lost. However, the bit in OPR[0] is not reset and RTSAN will be asserted again when an empty FIFO position is available. This feature can be used for flow control to prevent overrun in the receiver by using the RTSAN output signal to control the CTSN input of the transmitting device.
MR1A[5]--Channel A Error Mode Select This bit select the operating mode of the three FIFOed status bits (FE, PE, received break) for Channel A. In the `character' mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the `block' mode, the status provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last `reset error' command for Channel A was issued. MR1A[4:3|--Channel A Parity Mode Select If `with parity' or `force parity' is selected a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data MR1A[4:3] = 11 selects Channel A to operate in the special multi-drop mode described in the Operation section. MR1A[2]--Channel A Parity Type Select This bit selects the parity type (odd or even) if the `with parity' mode is programmed by MR1A[4:3], and the polarity of the forced parity bit if the `force parity' mode is programmed. It has no effect if the `no
2000 Jan 21
23
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
parity' mode is programmed. In the special multi-drop mode it selects the polarity of the A/D bit.
MR1A[1:0]--Channel A Bits Per Character Select This field selects the number of data bits per character to be transmitted and received. The character length does not include the start, parity, and stop bits.
MR2A--Channel A Mode Register 2
MR2A is accessed when the Channel A MR pointer points to MR2, which occurs after any access to MR1A. Accesses to MR2A do not change the pointer.
AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAA A A A AA A A AA A AA A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAA
Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MR2A/B 0x00 0x08 0 08 CHANNEL MODE 00 = Normal Tx CONTROLS RTS 0 = No 1 = Yes CTS ENABLE Tx 0 = No 1 = Yes STOP BIT LENGTH NOTE: Add 0.5 to binary codes 0-7 for 5 bit character lengths. 0 = 0.563 1 = 0.625 2 = 0.688 3 = 0.750 4 = 0.813 5 = 0.875 6 = 0.938 7 = 1.000 8 = 1.563 C = 1.813 D = 1.875 E = 1.938 F = 2.000 9 = 1.625 A = 1.688 B = 1.750 01 = Auto-Echo 10 = Local loop 11 = Remote loop NOTE: Add 0.5 to values shown for 0-7 if channel is programmed for 5 bits/char. MR2A[7:6]--Channel A Mode Select Each channel of the DUART can operate in one of four modes. MR2A[7:6] = 00 is the normal mode, with the transmitter and receiver operating independently. MR2A[7:6] = 11 selects remote loop back diagnostic mode. In this mode: 1. Received data is reclocked and retransmitted on the TxDA out-put. 2. The receive clock is used for the transmitter. 3. Received data is not sent to the local CPU, and the error status conditions are inactive. 4. The received parity is not checked and is not regenerated for transmission, i.e., transmitted parity is as received. 5. The receiver must be enabled. 6. Character framing is not checked, and the stop bits are retransmitted as received. 7. A received break is echoed as received until the next valid start bit is detected. The user must exercise care when switching into and out of the various modes. The selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. Likewise, if a mode is deselected the device will switch out of the mode immediately. An exception to this is switching out of auto echo or remote loop back modes: if the de-selection occurs just after the receiver has sampled the stop bit (indicated in auto echo by assertion of RxRDY), and the transmitter is enabled, the transmitter will remain in auto echo mode until the entire stop has been re-transmitted. MR2A[5]--Channel A Transmitter Request-to-Send Control This bit controls the deactivation of the RTSAN output (OP0) by the transmitter. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset automatically one bit time after the characters in the Channel A transmit shift register and in the TxFIFO, if any, are completely transmitted including the programmed number of stop bits, if the transmitter is not enabled. MR2A[7:6] = 01 places the channel in the automatic echo mode, which automatically retransmits the received data. The following conditions are true while in automatic echo mode: 1. Received data is reclocked and retransmitted on the TxDA output. 2. The receive clock is used for the transmitter. 3. The receiver must be enabled, but the transmitter need not be enabled. 4. The Channel A TxRDY and TxEMT status bits are inactive. 5. The received parity is checked, but is not regenerated for transmission, i.e. transmitted parity bit is as received. 6. Character framing is checked, but the stop bits are retransmitted as received. 7. A received break is echoed as received until the next valid start bit is detected. 8. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled. MR2A[7:6] = 10 selects local loop back diagnostic mode. In this mode: 1. The transmitter output is internally connected to the receiver input. 2. The transmit clock is used for the receiver. 3. The TxDA output is held High. 4. The RxDA input is ignored. 5. The transmitter must be enabled, but the receiver need not be enabled. 6. CPU to transmitter and receiver communications continue normally. 2000 Jan 21 24
MR2 MODE REGISTER 2
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
This feature can be used to automatically terminate the transmission of a message as follows ("line turnaround"): 1. Program auto-reset mode: MR2A[5] = 1. 2. Enable transmitter. 3. Asset RTSAN: OPR[0] = 1. 4. Send message. 5. Disable transmitter after the last character is loaded into the Channel A TxFIFO. 6. The last character will be transmitted and OPR[0] will be reset one bit time after the last stop bit, causing RTSAN to be negated. MR2A[4]--Channel A Clear-to-Send Control If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a 1, the transmitter checks the state of CTSAN (IPO) each time it is ready to send a character. If IPO is asserted (Low), the character is transmitted. If it is negated (High), the TxDA output remains in the marking state and the transmission is delayed until CTSAN goes low. Changes in CTSAN while a character is being transmitted do not affect the transmission of that character.. MR2A[3:0]--Channel A Stop Bit Length Select This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. In all cases, the receiver only checks for a `mark' condition at the center of the stop bit position (one half-bit time after the last data bit, or after the parity bit if enabled is sampled). If an external 1X clock is used for the transmitter, then MR2A[3] = 0 selects one stop bit and MR2A[3] = 1 selects two stop bits to be transmitted.
MR0B--Channel B Mode Register 0
MR0B is accessed when the Channel B MR pointer points to MR1. The pointer is set to MR0 by RESET or by a `set pointer' command applied via CRB. After reading or writing MR0B, the pointer will point to MR1B. The bit definitions for this register are identical to MR0A, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs. MR0B[3:0] are reserved.
MR1B--Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1. The pointer is set to MR1 by RESET or by a `set pointer' command applied via CRB. After reading or writing MR1B, the pointer will point to MR2B. The bit definitions for this register are identical to MR1A, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs.
MR2B--Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2, which occurs after any access to MR1B. Accesses to MR2B do not change the pointer. The bit definitions for mode register are identical to the bit definitions for MR2A, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs.
2000 Jan 21
25
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAA
2000 Jan 21
26
AAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAA
AAAAAA A A A A AA AAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAA AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAA
Addr CSR (7:4) CSR (3:0) CSRA/B 0x01 0x09 RECEIVER CLOCK SELECT See Text and table 5 TRANSMITTER CLOCK SELECT See Text and table 5
CSR CLOCK SELECT REGISTER
Table 5.
Baud rate (base on a 3.6864MHz crystal clock) MR0[0] = 0 (Normal Mode)
MR0[0] = 1 (Extended Mode I)
MR0[2] = 1 (Extended Mode II)
CSRA[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 0000 50 75 300 0001 110 110 110 0010 134.5 134.5 134.5 0011 200 150 1200 0100 300 300 1800 0101 600 600 3600 0110 1,200 1,200 7200 0111 1,050 2,000 1,050 1000 2,400 2,400 14.4K 1001 4,800 4,800 28.8K 1010 7,200 1,800 7,200 1011 9,600 9,600 57.6K 1100 38.4K 19.2K 230.4K 1101 Timer Timer Timer 1110 IP4-16X IP4-16X IP4-16X 1111 IP4-1X IP4-1X IP4-1X NOTE: The receiver clock is always a 16X clock except for CSRA[7:4] = 1111. CSRA[3:0]--Channel A Transmitter Clock Select This field selects the baud rate clock for the Channel A transmitter. The field definition is as shown in Table 5, except as follows: CSRA[3:0]
ACR[7] = 1 450 110 134.5 900 1800 3600 7,200 2,000 14.4K 28.8K 1,800 57.6K 115.2K Timer IP4-16X IP4-1X
ACR[7] = 0 4,800 880 1,076 19.2K 28.8K 57.6K 115.2K 1,050 57.6K 4,800 57.6K 9,600 38.4K Timer IP4-16X IP4-1X
ACR[7] = 1 7,200 880 1,076 14.4K 28.8K 57.6K 115.2K 2,000 57.6K 4,800 14.4K 9,600 19.2K Timer IP4-16X IP4-1X
CSRB--Channel B Clock Select Register
CSRB[7:4]--Channel B Receiver Clock Select This field selects the baud rate clock for the Channel B receiver. The field definition is as shown in Table 5, except as follows: CSRB[7:4]
1110
1111
IP3-16X
IP3-1X
1110
1111
The transmitter clock is always a 16X clock except for CSR[3:0] = 1111.
IP6-1X
IP6-16X
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
CSRB[3:0]--Channel B Transmitter Clock Select This field selects the baud rate clock for the Channel B transmitter. The field definition is as shown in Table 5, except as follows: CSRB[3:0]
1110
1111
IP5-1X
IP5-16X
The transmitter clock is always a 16X clock except for CSRB[3:0] = 1111.
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NOTE: Duty cycle of 16X clock is 50% "1% Crystal or Clock = 3.6864MHz
2000 Jan 21
Table 6. Bit rate generator characteristics
Philips Semiconductors
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
NORMAL RATE (BAUD)
38.4K
19.2K
134.5
9600
7200
4800
2400
2000
1800
1200
1050
600
300
200
150
110
75
50
ACTUAL 16X CLOCK (KHz)
32.056
16.756
614.4
307.2
153.6
2.153
1.759
115.2
76.8
38.4
28.8
19.2
9.6
4.8
3.2
2.4
1.2
0.8
27 ERROR (%) -0.260 -0.069 0.175 0.059 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Product specification
SC28L92
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
CRA--Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting, e.g., the `enable transmitter' and `reset transmitter' commands cannot be specified in a single command word.
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Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CRA/B 0x02 0x0A MISCELLANEOUS COMMANDS Disable Tx 1 = Yes 0 = No Enable Tx 1 = Yes 0 = No Disable Rx 1 = Yes 0 = No Enable Rx 1 = Yes 0 = No See Text of Channel Command Register NOTES: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded. CRA[7:4]--Miscellaneous Commands Execution of the commands in the upper four bits of this register must be separated by 3 X1 clock edges. Other reads or writes (including writes tot he lower four bits) may be inserted to achieve this separation. CRA[7:4]--Commands 0000 0001 0010 No command. Reset MR pointer. Causes the Channel A MR pointer to point to MR1. Reset receiver. Resets the Channel A receiver as if a hardware reset had been applied. The receiver is disabled and the FIFO is flushed. Reset transmitter. Resets the Channel A transmitter as if a hardware reset had been applied. Reset error status. Clears the Channel A Received Break, Parity Error, and Overrun Error bits in the status register (SRA[7:4]). Used in character mode to clear OE status (although RB, PE and FE bits will also be cleared) and in block mode to clear all error status after a block of data has been received. Reset Channel A break change interrupt. Causes the Channel A break detect change bit in the interrupt status register (ISR[2]) to be cleared to zero Start break. Forces the TxDA output Low (spacing). If the transmitter is empty the start of the break condition will be delayed up to two bit times. If the transmitter is active the break begins when transmission of the character is completed. If a character is in the TxFIFO, the start of the break will be delayed until that character, or any other loaded subsequently are transmitted. The transmitter must be enabled for this command to be accepted. Stop break. The TxDA line will go High (marking) within two bit times. TxDA will remain High for one bit time before the next character, if any, is transmitted. Assert RTSN. Causes the RTSN output to be asserted (Low). Negate RTSN. Causes the RTSN output to be negated (High) 1111 1101 1110 1011 1100 1010 Set Timeout Mode On. The receiver in this channel will restart the C/T as each receive character is transferred from the shift register to the RxFIFO. The C/T is placed in the counter mode, the START/STOP counter commands are disabled, the counter is stopped, and the Counter Ready Bit, ISR[3], is reset. (See also Watchdog timer description in the receiver section.) Set MR pointer to `0' Disable Timeout Mode. This command returns control of the C/T to the regular START/STOP counter commands. It does not stop the counter, or clear any pending interrupts. After disabling the timeout mode, a `Stop Counter' command should be issued to force a reset of the ISR(3) bit Not used. Power Down Mode On. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable power down mode (1111) requires a X1/CLK. While in the power down mode, do not issue any commands to the CR except the disable power down mode command. The contents of all registers will be saved while in this mode. . It is recommended that the transmitter and receiver be disabled prior to placing the DUART into power down mode. This command is in CRA only. Disable Power Down Mode. This command restarts the oscillator. After invoking this command, wait for the oscillator to start up before writing further commands to the CR. This command is in CRA only. For maximum power reduction input pins should be at VSS or VDD. 0011 0100 0101 0110 0111 CRA[3]--Disable Channel A Transmitter This command terminates transmitter operation and reset the TxDRY and TxEMT status bits. However, if a character is being transmitted or if a character is in the TxFIFO when the transmitter is disabled, the transmission of the character(s) is completed before assuming the inactive state. CRA[2]--Enable Channel A Transmitter Enables operation of the Channel A transmitter. The TxRDY and TxEMT status bits will be asserted if the transmitter is idle. 1000 1001 2000 Jan 21 28
CR COMMAND REGISTER
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
CRA[1]--Disable Channel A Receiver This command terminates operation of the receiver immediately--a character being received will be lost. The command has no effect on the receiver status bits or any other control registers. If the special multi-drop mode is programmed, the receiver operates even if it is disabled. See Operation section. CRA[0]--Enable Channel A Receiver Enables operation of the Channel A receiver. If not in the special wakeup mode, this also forces the receiver into the search for start-bit state.
CRB--Channel B Command Register
CRB is a register used to supply commands to Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the `enable transmitter' and `reset transmitter' commands cannot be specified in a single command word. The bit definitions for this register are identical to the bit definitions for CRA, with the exception of commands "Ex" and "Fx" which are used for power down mode. These two commands are not used in CRB. All other control actions that apply to CRA also apply to CRB.
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAA A A A A A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A
Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SRA/B 0x01 0x09 RECEIVED BREAK* 0 = No 1 = Yes FRAMING ERROR* 0 = No 1 = Yes PARITY ERROR* 0 = No 1 = Yes OVERRUN ERROR 0 = No 1 = Yes TxEMT TxRDY FFULL RxRDY 0 = No 1 = Yes 0 = No 1 = Yes 0 = No 1 = Yes 0 = No 1 = Yes *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a "reset error status" command. In character mode they are discarded when the corresponding data character is read from the FIFO. In block error mode, the error-reset command (command 4x or receiver reset )must used to clear block error conditions SRA[7]--Channel A Received Break This bit indicates that an all zero character of the programmed length has been received without a stop bit. Only a single FIFO position is occupied when a break is received: further entries to the FIFO are inhibited until the RxDA line returns to the marking state for at least one-half a bit time two successive edges of the internal or external 1X clock. This will usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. When this bit is set, the Channel A `change in break' bit in the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break condition, as defined above, is detected. The break detect circuitry can detect breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. This bit is reset by command 4 (0100) written to the command register or by receiver reset. SRA[6]--Channel A Framing Error This bit, when set, indicates that a stop bit was not detected (not a logical 1) when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. SRA[5]--Channel A Parity Error This bit is set when the `with parity' or `force parity' mode is programmed and the corresponding character in the FIFO was received with incorrect parity. In the special multi-drop mode the parity error bit stores the receive A/D (Address/Data) bit. SRA[4]--Channel A Overrun Error This bit, when set, indicates that one or more characters in the received data stream have been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. This bit is cleared by a `reset error status' command. SRA[3]--Channel A Transmitter Empty (TxEMTA) This bit will be set when the transmitter under runs, i.e., both the TxEMT and TxRDY bits are set. This bit and TxRDY are set when the transmitter is first enabled and at any time it is re-enabled after either (a) reset, or (b) the transmitter has assumed the disabled state. It is always set after transmission of the last stop bit of a character if no character is in the THR awaiting transmission. It is reset when the THR is loaded by the CPU, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the under run condition. SRA[2]--Channel A Transmitter Ready (TxRDYA) This bit, when set, indicates that the transmit FIFO is not full and ready to be loaded with another character. This bit is cleared when the transmit FIFO is loaded by the CPU and there are (after this load) no more empty locations in the FIFO. It is set when a character is transferred to the transmit shift register. TxRDYA is reset when the transmitter is disabled and is set when the transmitter is first enabled. Characters loaded to the TxFIFO while this bit is 0 will be lost. This bit has different meaning from ISR[0]. SRA[1]--Channel A FIFO Full (FFULLA) This bit is set when a character is transferred from the receive shift register to the receive FIFO and the transfer causes the FIFO to become full, i.e., all eight (or 16) FIFO positions are occupied. It is reset when the CPU reads the receive FIFO. If a character is waiting in the receive shift register because the FIFO is full, FFULLA will not be reset when the CPU reads the receive FIFO. This bit has different meaning from ISR1 when MR1 6 is programmed to a `1'. SRA[0]--Channel A Receiver Ready (RxRDYA) This bit indicates that a character has been received and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset 2000 Jan 21 29
SR STATUS REGISTER Channel A Status Register
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
when the CPU reads the receive FIFO, only if (after this read) there are no more characters in the FIFO - the Rx FIFO becomes empty.
SRB--Channel B Status Register
The bit definitions for this register are identical to the bit definitions for SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and outputs.
OPCR--Output Port Configuration Register
A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA A AAAAAAA A A A A A A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA
Addr Bit 7 OP7 BIT 6 OP6 BIT 5 OP5 BIT 4 OP4 BIT 3 OP3 00 01 10 11 BIT 2 OP2 BIT 1 OP1 00 01 10 11 BIT 0 OP0 OPCR 0x0D 0 = OPR[7] 1 = TxRDY B 0 = OPR[6] 1 = TxRDY A 0 = OPR[5] 1 = RxRDY/FFULL B 0 = OPR[4] 1 = RxRDY/FFULL A = OPR[3] = C/T OUTPUT = TxCB(1X) = RxCB(1X) = OPR[2] = TxCA(16X) = TxCA(1X) = RxCA(1X) OPCR[7]--OP7 Output Select This bit programs the OP7 output to provide one of the following: 0 1 The complement of OPR[7]. The Channel B transmitter interrupt output which is the complement of ISR[4]. When in this mode OP7 acts as an open-drain output. Note that this output is not masked by the contents of the IMR. OPCR[3:2]--OP3 Output Select This bit programs the OP3 output to provide one of the following: 00 01 The complement of OPR[3]. The counter/timer output, in which case OP3 acts as an open-drain output. In the timer mode, this output is a square wave at the programmed frequency. In the counter mode, the output remains High until terminal count is reached, at which time it goes Low. The output returns to the High state when the counter is stopped by a stop counter command. Note that this output is not masked by the contents of the IMR. The 1X clock for the Channel B transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output. The 1X clock for the Channel B receiver, which is the clock that samples the received data. If data is not being received, a free running 1X clock is output. OPCR[6]--OP6 Output Select This bit programs the OP6 output to provide one of the following: 0 1 The complement of OPR[6]. The Channel A transmitter interrupt output which is the complement of ISR[0]. When in this mode OP6 acts as an open-drain output. Note that this output is not masked by the contents of the IMR. 10 11 OPCR[5]--OP5 Output Select This bit programs the OP5 output to provide one of the following: 0 1 The complement of OPR[5]. The Channel B receiver interrupt output which is the complement of ISR[5]. When in this mode OP5 acts as an open-drain output. Note that this output is not masked by the contents of the IMR. 00 01 The complement of OPR[2]. The 16X clock for the Channel A transmitter. This is the clock selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] = 1111. The 1X clock for the Channel A transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output. The 1X clock for the Channel A receiver, which is the clock that samples the received data. If data is not being received, a free running 1X clock is output. OPCR[1:0]--OP2 Output Select This field programs the OP2 output to provide one of the following: OPCR[4]--OP4 Output Select This field programs the OP4 output to provide one of the following: 0 1 The complement of OPR[4]. The Channel A receiver interrupt output which is the complement of ISR[1]. When in this mode OP4 acts as an open-drain output. Note that this output is not masked by the contents of the IMR. 10 11 2000 Jan 21 30
OPCR OUTPUT PORT CONFIGURATION REGISTER
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
SOPR--Set the Output Port Bits (OPR)
AAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A AAAAA AAAAAAAA AAAAAAAAAAAAAAA A AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A
Addr Bit 7 BIT 6 OP 6 BIT 5 OP 5 BIT 4 OP 4 BIT 3 OP 3 BIT 2 OP 2 BIT 1 OP 1 BIT 0 OP 0 SOPR 0x0E OP 7 1=set bit 0 = no change 1=set bit 0 = no change 1=set bitAAAAA 1=set bit 1=set bit 0 = no 0 = no 0 = no change change change 1=set bitAAAAA 1=set bit 1=set bit 0 = no 0 = no 0 = no change change change
SOPR[7:0]--Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows software to set individual bits with our keeping a copy of the OPR bit configuration.
ROPR--Reset Output Port Bits (OPR)
AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAA A A A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAAAAAAAAA AAAAAAAA AAAAAAAA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A
AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAA A A A A A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A
Addr ROPR 0x0F Bit 7 OP 7 1=reset bit 0 = no change BIT 6 OP 6 1=reset bit 0 = no change BIT 5 OP 5 1=reset bit 0 = no change BIT 4 OP 4 1=reset bit 0 = no change BIT 3 OP 3 1=reset bit 0 = no change BIT 2 OP 2 1=reset bit 0 = no change BIT 1 OP 1 1=reset bit 0 = no change BIT 0 OP 0 1=reset bit 0 = no change
ROPR[7:0]--Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This allows software to reset individual bits with our keeping a copy of the OPR bit configuration.
OPR Output Port Register
Addr N/A N/A Bit 7
The output pins (OP pins) drive the compliment of the data in this register as controlled by SOPR and ROPR. BIT 6 OP 6 BIT 5 OP 5 BIT 4 OP 4 BIT 3 OP 3 BIT 2 OP 2
BIT 1 OP 1
BIT 0 OP 0
OP 7
0 = Pin HighAAAAA Pin High 0 = Pin High 0= 1 = Pin Low 1 = Pin Low 1 = Pin Low
0 = Pin HighAAAAA= Pin High 0 = Pin High 0 1 = Pin Low 1 = Pin Low 1 = Pin Low
0 = Pin High 1 = Pin Low
0 = Pin High 1 = Pin Low
2000 Jan 21
31
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
AAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAA AAAAAA A AAAAAAAAAAAAAAAAA AAAAAA A AA AAAAAAAAAAAAAAAAA AAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA AAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAA A A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A
Addr ACR Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BRG SET Select 0 = set 1 1 = set 2 Counter Timer Mode Mode and clock sour select See table 7 Delta IP3 int enable 0 = off 1 = enabled Delta IP3 int enable 0 = off 1 = enabled Delta IP3 int enable 0 = off 1 = enabled Delta IP3 int enable 0 = off 1 = enabled 0x04
ACR Auxiliary Control Register
ACR--Auxiliary Control Register
Table 7. ACR 6:4 field definition
ACR 6:4 000 001 010 011 MODE
ACR[7]--Baud Rate Generator Set Select This bit selects one of two sets of baud rates to be generated by the BRG (see Table 5). The selected set of rates is available for use by the Channel A and B receivers and transmitters as described in CSRA and CSRB. Baud rate generator characteristics are given in Table 6. ACR[6:4]--Counter/Timer Mode And Clock Source Select This field selects the operating mode of the counter/timer and its clock source as shown in Table 7
CLOCK SOURCE
Counter Counter Counter Counter Timer Timer
External (IP2)
TxCA - 1X clock of Channel A transmitter TxCB - 1X clock of Channel B transmitter
Crystal or external clock (X1/CLK) divided by 16 External (IP2)
100 101 110 111
External (IP2) divided by 16
ACR [3:0]--IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable This field selects which bits of the input port change register (IPCR) cause the input change bit in the interrupt status register (ISR [7]) to be set. If a bit is in the `on' state the setting of the corresponding bit in the IPCR will also result in the setting of ISR [7], which results in the generation of an interrupt output if IMR [7] = 1. If a bit is in the `off' state, the setting of that bit in the IPCR has no effect on ISR [7]. NOTE: The timer mode generates a square wave
TimerAAAAAAAAAAAA Crystal or external clock (X1/CLK) Timer Crystal or external clock (X1/CLK) divided by 16
IPCR INPUT PORT CHANGE REGISTER
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AA A AA A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A A AA A AA A A
IPCR 0x04 Delta IP3 0 = no change Delta IP3 0 = no change Delta IP3 0 = no change Delta IP3 0 = no change IP 3 IP 2 IP 1 IP 0 0 = low 0 = low 0 = low 0 = low 1 = change 1 = change 1 = change 1 = change 1 = High 1 = High 1 = High 1 = High IPCR [7:4]--IP3, IP2, IP1, IP0 Change-of-State These bits are set when a change-of-state, as defined in the input port section of this data sheet, occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR [7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. IPCR [3:0]--IP3, IP2, IP1, IP0 Change-of-State These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. 2000 Jan 21 32
Addr
Bit 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
ISR--Interrupt Status Register
This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a `1' and the corresponding bit in the IMR is also a `1', the INTRN output will be asserted (Low). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR - the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H`00' when the DUART is reset.
ISR INTERRUPT STATUS REGISTER
AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AA A AA A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Addr ISR Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INPUT PORT CHANGE DELTA Break B RxRDY/ FFULL B TxRDY B Counter Ready Delta Break A RxRDY/ FFULL A TxRDY A 0x05 0 = not active 1 = active 0 = not active 1 = active 0 = not active 1 = active 0 = not active 1 = active 0 = not active 1 = active 0 = not active 1 = active 0 = not active 1 = active 0 = not active 1 = active ISR[7]--Input Port Change Status This bit is a `1' when a change-of-state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR. ISR[6]--Channel B Change In Break This bit, when set, indicates that the Channel B receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel B `reset break change interrupt' command. ISR[5]--RxB Interrupt This bit indicates that the channel B receiver is interrupting according to the fill level programmed by the MR0 and MR1 registers. This bit has a different meaning than the receiver ready/full bit in the status register. ISR[4]--TxB Interrupt This bit indicates that the channel B transmitter is interrupting according to the interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning than the Tx RDY bit in the status register. ISR[3]--Counter Ready. In the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated square wave (every other time that the counter/timer reaches zero count). The bit is reset by a stop counter command. The command, however, does not stop the counter/timer. ISR[2]--Channel A Change in Break This bit, when set, indicates that the Channel A receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel A `reset break change interrupt' command. ISR[1]--RxA Interrupt This bit indicates that the channel A receiver is interrupting according to the fill level programmed by the MR0 and MR1 registers. This bit has a different meaning than the receiver ready/full bit in the status register. ISR[0]--TxA Interrupt This bit indicates that the channel A transmitter is interrupting according to the interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning than the Tx RDY bit in the status register.
IMR--Interrupt Mask Register
The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a `1' and the corresponding bit in the IMR is also a `1' the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs OP3-OP7 or the reading of the ISR.
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAA A A A A A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A
Addr IMR Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INPUT PORT CHANGE 0 = not enabled Delta Break B 0 = not enabled RxRDY/ FFULL B 0 = not enabled TxRDY B Counter Ready 0 = not enabled Delta Break A 0 = not enabled RxRDY/ FFULL A 0 = not enabled TxRDY A 0x05 0 = not enabled 0 = not enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled 2000 Jan 21 33
IMR INTERRUPT MASK REGISTER
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
A A AAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A
IVR/GP 0x0C Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Interrupt Vector Register (68XXX mode) or General Purpose register (80XXX mode) This register stores the Interrupt Vector. It is initialized to 0x0F on hardware reset and is usually changed from this value during initialization of the SC26L92. The contents of this register will be placed on the data bus when IACKN is asserted low or a read of address 0xC is performed. When not operating in the 68XXX mode, this register may be used as a general purpose one byte storage register. A convenient use could be to store a "shadow" of the contents of another SC28L92 register (IMR, for example).
IVR/GP - Interrupt Vector Register (68XXX mode) or General Purpose register (80XXX mode)
CTPU and CTPL - Counter/Timer Registers
A A AAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A A AAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A
CTPU 0x06 Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 The lower eight (8) bits for the 16 bit counter timer preset register
CTPU COUNTER TIMER PRESET UPPER
CTPL COUNTER -TIMER PRESET LOW
CTPL 0x07 Bit 7 BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
The Upper eight (8) bits for the 16 bit counter timer preset register
The CTPU and CTPL hold the eight MSBs and eight LSBs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. The minimum value which may be loaded into the CTPU/CTPL registers is H`0002'. Note that these registers are write-only and cannot be read by the CPU.
new values have not been loaded, the previous count values are preserved and used for the next count cycle.
In the timer mode, the C/T generates a square wave whose period is twice the value (in C/T clock periods) of the CTPU and CTPL. The waveform so generated is often used for a data clock. The formula for calculating the divisor n to load to the CTPU and CTPL for a particular 1X data clock is shown below. n = (C/T Clock Frequency) divided by (2 x 16 x Baud rate desired) Often this division will result in a non-integer number; 26.3, for example. One can only program integer numbers in a digital divider. Therefore, 26 would be chosen. This gives a baud rate error of 0.3/26.3 which is 1.14%; well within the ability asynchronous mode of operation. The C/T will not be running until it receives an initial `Start Counter' command (read at address A3-A0 = 1110). After this, while in timer mode, the C/T will run continuously. Receipt of a start counter command (read with A3-A0 = 1110) causes the counter to terminate the current timing cycle and to begin a new cycle using the values in CTPU and CTPL. If the value in CTPU and CTPL is changed, the current half-period will not be affected, but subsequent half periods will be affected. The counter ready status bit (ISR[3]) is set once each cycle of the square wave. The bit is reset by a stop counter command (read with A3-A0 = H'F'). The command however, does not stop the C/T. The generated square wave is output on OP3 if it is programmed to be the C/T output. In the counter mode, the value C/T loaded into CTPU and CTPL by the CPU is counted down to 0.. Counting begins upon receipt of a start counter command. Upon reaching terminal count 0x0000, the counter ready interrupt bit (ISR[3]) is set. The counter continues counting past the terminal count until stopped by the CPU. If OP3 is programmed to be the output of the C/T, the output remains High until terminal count is reached, at which time it goes Low. The output returns to the High state and ISR[3] is cleared when the counter is stopped by a stop counter command. The CPU may change the values of CTPU and CTPL at any time, but the new count becomes effective only on the next start counter commands. If 2000 Jan 21 34
In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTL) may be read by the CPU. It is recommended that the counter be stopped when reading to prevent potential problems which may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. However, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in CTPU and CTPL. When the C/T clock divided by 16 is selected, the maximum divisor becomes 1,048,575.
Output Port Notes
The output ports are controlled from four places: the OPCR register,the OPR register, the MR registers and the command register (except the 2681 and 68681) The OPCR register controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register. The content of the OPR register is controlled by the "Set Output Port Bits Command" and the "Reset Output Bits Command". These commands are at E and F, respectively. When these commands are used, action takes place only at the bit locations where ones exist. For example, a one in bit location 5 of the data word used with the "Set Output Port Bits" command will result in OPR5 being set to one. The OP5 would then be set to zero (V SS ). Similarly, a one in bit position 5 of the data word associated with the "Reset Output Ports Bits" command would set OPR5 to zero and, hence, the pin OP5 to a one (VDD).
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. The CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal is active low; thus, it is called CTSAN for TxA and CTSBN for TxB. RTS is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. It is also active low and is,
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin OP0 and RTSBN is on OP1. A receiver's RTS output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say that RTS and CTS are different ends of the same wire! MR2(4) is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input is driven high, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of
the receiver that will be connected to the transmitter's CTS input. The receiver will set RTS high when the receiver FIFO is full AND the start bit of the ninth or 17th character is sensed. Transmission then stops with nine or 17 valid characters in the receiver. When MR2(4) is set to one, CTSN must be at zero for the transmitter to operate. If MR2(4) is set to zero, the IP pin will have no effect on the operation of the transmitter. MR1(7) is the bit that allows the receiver to control OP0. When OP0 (or OP1) is controlled by the receiver, the meaning of that pin will be.
RESETN RESETN
tRES
tRES
80XXX Mode
68XXX Mode
SD00696
Figure 4. Reset Timing
A0-A3
tAS tAH CEN tCS tRW RDN tCH tRWD
tDD D0-D7 (READ) NOT VALID
tDF
FLOAT
VALID
FLOAT
tRWD WDN
tDS tDH D0-D7 (WRITE) VALID
SD00087
Figure 5. Bus Timing (80XXX mode)
2000 Jan 21
35
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
tCSC X1/CLK tAS A1-A4 tCS RWN CSN tAH tDD D0-D7 tDA DTACKN tDCR tDAH tDAT NOT VALID DATA VALID tRWD tCH
tDF
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
SD00687
Figure 6. Bus Timing (Read Cycle) (68XXX mode)
tCSC X1/CLK tAS A1-A4 tCS tCH
RWN
CSN
tAH
tRWD
D0-D7 tDS DTACKN tDCW tDAT NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. tDAH tDH
SD00688
Figure 7. Bus Timing (Write Cycle) (68XXX mode)
2000 Jan 21
36
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
tCSC X1/CLK
INTRN
IACKN
tDD D0-D7 tCSD tDAL DTACKN tDCR NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. tDAH tDAT
tDF
SD00149
Figure 8. Interrupt Cycle Timing (68XXX mode)
RDN
tPS
tPH
IP0-IP6
(a) INPUT PINS
WRN
tPD
OP0-OP7
OLD DATA
NEW DATA
(b) OUTPUT PINS
SD00135
Figure 9. Port Timing
2000 Jan 21
37
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
WRN
VM
tIR INTERRUPT 1 OUTPUT VOL +0.5V VOL
RDN
VM
tIR INTERRUPT 1 OUTPUT VOL +0.5V VOL NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. SD00136
Figure 10. Interrupt Timing (80xxx mode)
tCLK tCTC tRx tTx X1/CLK CTCLK RxC TxC tCLK tCTC tRx tTx
VCC NOTE: RESISTOR REQUIRED FOR TTL INPUT. CLK
470
X1
*NOTE: X2 MUST BE LEFT OPEN.
X2*
3pF PARASITIC CAPACITANCE
SC28L92 X1 2pF
C1 50k to 100k C2
X2 3pF PARASITIC CAPACITANCE 3.6864MHz
4pF
TO UART CIRCUIT
C1 = C2 24pF FOR CL = 20pF C1 and C2 should be chosen according to the crystal manufacturer's specification. C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins. Gain at 3.6864MHz: 9 to 13 dB Package capacitance approximately 4pF.
SD00695
Figure 11. Clock Timing
2000 Jan 21
38
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT)
tTXD
TxD
tTCS
TxC (1X OUTPUT)
SD00138
Figure 12. Transmitter External Clocks
RxC (1X INPUT)
tRXS
tRXH
RxD
SD00139
Figure 13. Receiver External Clock
TxD TRANSMITTER ENABLED TxRDY (SR2)
D1
D2
D3
BREAK
D4
D6
WRN D1 CTSN1 (IP0) D8 D9 START BREAK D10 STOP BREAK D11 WILL NOT BE WRITTEN TO THE TxFIFO D12
RTSN2 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR2(4) = 1. 2. Timing shown for MR2(5) = 1. OPR(0) = 1
SD00155
Figure 14. Transmitter Timing
2000 Jan 21
39
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
RxD
D1
D2
D8
D9
D10
D11
D12
D13
RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL (OP5)2 RDN STATUS DATA D1 OVERRUN (SR4) RTS1 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1. 2. Shown for OPCR(4) = 1 and MR(6) = 0. D11 WILL BE LOST DUE TO OVERRUN
D12, D13 WILL BE LOST DUE TO RECEIVER DISABLE.
STATUS DATA STATUS DATA STATUS DATA D2 D3 D10 RESET BY COMMAND
SD00156
Figure 15. Receiver Timing
MASTER STATION TxD
BIT 9 ADD#1 1 D0
BIT 9 0
BIT 9 ADD#2 1
TRANSMITTER ENABLED TxRDY (SR2)
WRN MR1(4-3) = 11 MR1(2) = 1 ADD#1 MR1(2) = 0 D0 MR1(2) = 1 ADD#2
PERIPHERAL STATION BIT 9 RxD RECEIVER ENABLED RxRDY (SR0) RDN/WRN MR1(4-3) = 11 0
BIT 9 ADD#1 1 D0
BIT 9 0
BIT 9 ADD#2 1
BIT 9 0
ADD#1
STATUS DATA D0
STATUS DATA ADD#2
SD00096
Figure 16. Wake-Up Mode
2000 Jan 21
40
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
I = 2.4mA INTRN DACKN 125pF I = 2.4mA VOL return to VCC for a 0 level I = 400A VOH return to VSS for a 1 level +5V
D0-D7 TxDA/B OP0-OP7 125pF
SD00690
Figure 17. Test Conditions on Outputs
2000 Jan 21
41
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
2000 Jan 21
42
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
2000 Jan 21
43
Philips Semiconductors
Product specification
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)
SC28L92
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 01-00 Document order number: 9397 750 06796
Philips Semiconductors
2000 Jan 21 44

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